Structure and fabrication of self-aligned high-performance organic fets

ABSTRACT

A low channel length organic field-effect transistor can be produced in high volume and at low cost. The transistor structure includes successively deposited patterned layers of a first conductor layer acting as a source terminal, a first dielectric layer, a second conductor layer acting as a drain terminal, a semiconductor layer, a second dielectric layer, and a third conductor layer acting as the gate terminal. In this structure, the transistor is formed on the edge of the first dielectric between the first conductor layer and the second conductor layer. The second conductor layer is deposited on the raised surfaces formed by the dielectric such that conductive ink does not flow into the trough between the dielectric raised surfaces. This is accomplished by coating a flat or rotary print plate with the conductive ink, and applying the appropriate pressure to deposit the materials only on the raised surfaces of the dielectric. The second metal is automatically aligned to the layer beneath it. Due to this self-alignment and the short channel formed by the thickness of the dielectric material, a high-performance FET is produced without the requirement of high-resolution lithography equipment.

1. FIELD OF INVENTION

The present invention relates to organic transistors and, moreparticularly, to a structure and method of fabricating high performingorganic FETs utilizing an efficient high volume self-aligned patterningtechnique to produce low channel length organic FET devices.

2. DESCRIPTION OF RELATED ART

Organic field-effect transistors (oFETs) have been proposed for a numberof applications including displays, electronic barcodes and sensors. Lowcost processes, large-area circuits and the chemically active nature oforganic materials are the chief driving forces to make OFETs importantin various applications. Many of these objectives depend on a method offabrication utilizing printing techniques such as flexography, gravure,silk screen and inkjet printing.

Organic MOS transistors are similar to silicon metal-oxide-semiconductortransistors in operation. The major difference in construction is thatthe organic MOS transistor utilizes a thin layer of a semiconductingorganic polymer film to act as the semiconductor of the device, asopposed to a silicon layer as used in the more typical in-organicsilicon MOS device.

Referring now to FIG. 1, a cross-sectional diagram of a top-gate bottomcontact organic MOS transistor 100 is shown. Two conductor regions 101and 102 are deposited and patterned on substrate 112. The gap betweenconductive regions 101 and 102 is known as the “channel”, and isdesignated as 103 in FIG. 1. A semiconductor layer 104 is deposited onthe conductive regions 101 and 102. A thin film of dielectric material106 is deposited on top of semiconductor layer 104. A conductive film108 is deposited and patterned on top of organic semiconductor 106 toform the gate, such the gate completely overlaps the channel region 103.

Through an electrical field effect, a voltage is applied between gateconductor 108 and source 101 modifies the resistance of the organicsemiconductor in the channel region 103 in the vicinity of the interfacebetween the semiconductor region 104 and the dielectric 106. Whenanother voltage is applied between source 101 and drain 102, a currentflows between the drain and the source that depends on both thegate-to-source and the drain-to-source voltages.

Organic semiconductor materials are often classified as polymeric, lowmolecular weight, or hybrid. Pentacene, hexithiphene, TPD, and PBD areexamples of low weight molecules. Polythiophene, parathenylene vinylene,and polyphenylene ethylene are examples of polymeric semiconductors.Polyvinyl carbazole is an example of a hybrid material. These materialsare not classified as insulators or conductors. Organic semiconductorsbehave in a manner that can be described in terms analogous to the bandtheory in inorganic semiconductors. However, the actual mechanics givingrise to charge carriers in organic semiconductors are substantiallydifferent from inorganic semiconductors. In inorganic semiconductors,such as silicon, carriers are generated by introducing atoms ofdifferent valencies into a host crystal lattice, the quantity of whichis described by the number of carriers that are injected into theconduction band, and the motion of which can be described by a wavevector k. In organic semiconductors, carriers are generated in certainmaterials by the hybridization of carbon molecules in which weaklybonded electrons, called π electrons, become delocalized and travelrelatively long distances from the atom which originally gave rise tothe electron. This effect is particularly noted in materials comprisingconjugated molecules or benzene ring structures. Because of thedelocalization, these it electrons can be loosely described as being ina conduction band. This mechanism gives rise to a low charge mobility, ameasure describing the speed with which these carriers can move throughthe semiconductor, resulting in dramatically lower currentcharacteristics of organic semiconductors in comparison to inorganicsemiconductors.

Besides a lower mobility, the physics of carrier generation gives riseto another key difference between the operation of an organic MOStransistor and inorganic semiconductor. In the typical operation of aninorganic semiconductor, the resistance of the channel region ismodified by an “inversion layer” consisting of the charge carriers madeup of the type of charge that exists as a minority in the semiconductor.The silicon bulk is doped with the opposite type of carrier as comparedto that used for conduction. For example, a p-type inorganicsemiconductor is built with an n-type semiconductor, but uses p-typecarriers, also called holes, to conduct current between the source anddrain. In the typical operation of an organic semiconductor, however,the resistance of the channel region is modified by an “accumulationlayer” consisting of charge carriers made up of the type of charge thatexists as a majority in the semiconductor. For example, a PMOS organictransistor uses a P-type semiconductor and p-carriers, or holes, togenerate the current in typical operation.

Though organic transistors have much lower performance than inorganictransistors, the materials and processing techniques to produce organictransistors cost significantly less those used to produce inorganictransistors. Therefore, organic transistor technology has applicationwhere low cost is desired and low performance is acceptable. Theperformance of a transistor, both organic and inorganic, depends in parton the channel length, defined as the space between and source anddrain. The maximum frequency of operation is inversely proportional tothe square of this channel length. Therefore, it is desirable to reducethis space as much as possible. Low cost printing techniques aregenerally limited to a minimum range of 25μ. Printing at resolutionsfiner than this is generally not possible.

In the prior art, transistors structures wherein the source and drainare vertical to each other have been proposed. This type of structurehas the advantage that a small gap between the source and drain can beachieved without having to print at such high resolution. FIG. 2illustrates the basic structure. The first conductor metal-source 204and second conductor metal-drain 206 are deposited on either side of afirst dielectric layer 208. The channel of the transistor is defined bythe surface 209 between the first metal and the second metal conductors,thereby defining the channel length by the thickness of the firstdielectric. A second dielectric 207 and a third conductor 214 are thendeposited on that surface to complete the transistor. A high performanceshort-channel length transistor has thereby been produced without theneed to print the short gap between the source and drain.

A key to successful implementation of this structure is the alignment ofmetal-drain 206 and the beginning of the slope 211 of first dielectric208.

FIG. 3 illustrates the consequences of poor alignment betweenmetal-drain 306 and the underlying first dielectric layer 308. Whenlayers are aligned, there is always an alignment tolerance whichspecifies the accuracy by which one layer can be produced with respectto another layer below it. If the conductor is printed onto the slope,the ink will flow to short to the metal-source 304, rending thetransistor nonfunctional. Therefore, it is necessary to allow atolerance from the edge of the slope so that it can be guaranteed thatthe ink will not print on the slope 309 of dielectric 308. Consequently,the metal-drain layer 306 must be produced allowing a gap on the surfaceof dielectric 308 to ensure that in the worse case misalignment, themetal-drain 306 layer falls on point 311 at the edge of the dielectricslope 309. However, the channel length of the nominal device is nowdefined by the total distance between metal-drain 306 and metal-source304, which now is now the slope 309 plus the gap 313 on the surface ofdielectric 308. Since the alignment tolerance is likely to be largecompared to the thickness of dielectric 308, the additional gap 313 islikely to be quite large in comparison. The advantages of the shortchannel length that can potentially be obtained through verticaltransistors is consequently lost. For this reason, an effective verticaltransistor requires a process that eliminates this alignment tolerance.

One such method known in the prior art to eliminate this alignmenttolerance is described by Natalie Stutzmann, Richard Friend, and HenningSirringhause in Science on Mar. 21, 2004 in an article entitled“Self-Aligned, Vertical-Channel Polymer Field-Effect Transistors.” FIG.4 illustrates the methodology by which this is done. Referring to FIG.4, a V-shaped impression die 410 is pressed through previously depositedlayers consisting of first metal metal-source 404, first dielectric 406,and second metal 408. When the impression die 410 is lifted, a cut ismade through the layers forming a sloped dielectric 406 while cuttingthe second metal 408 at the top of the dielectric slope. However,several issues make this fabrication method impractical. A seriousproblem with this method is that the metal 408 layer smears whenpressing the impression die through the layers, thereby shorting secondconductor 408 and first conductor 404. Another problem with this methodis that the die impression forms a point at the bottom of the device,which is very difficult to deposit layers of controlled thickness inthis region. One further problem with this method is that pressurecontrols the impression die depth of penetration. If the impression diepressure is too light, the impression will not penetrate to the firstmetal layer 404. If the impression die pressure is too heavy, theimpression die will penetrate substrate 402, adversely affecting theperformance of the transistors. The range of pressure is thereforedefined by the thickness of the first conductor 404, a pressurevariation that is too narrow for high-volume low-cost manufacturingmethods.

What is desired, therefore, is a practical structure for an organic FETthat brings about a small channel length utilizing low cost printingtechniques.

SUMMARY OF THE INVENTION

According to the present invention, a structure and method offabrication is disclosed that can produce low channel length devices inhigh volume and at low cost. The structure includes successivelydeposited patterned layers of a first conductor layer acting as a sourceterminal, a first dielectric layer, a second conductor layer acting as adrain terminal, a semiconductor layer, a second dielectric layer, and athird conductor layer acting as the gate terminal. In this structure,the transistor is formed on the edge of the first dielectric between thefirst conductor layer and the second conductor layer.

The second conductor layer is deposited on the raised surfaces formed bythe dielectric such that the ink does not flow into the trough betweenthe dielectric raised surfaces. In an embodiment of the invention, thisis accomplished by coating a flat or rotary print plate with aconductive ink, and applying the appropriate pressure to deposit thematerials only on the raised surfaces of the dielectric. In this manner,the second metal is automatically aligned to the layer beneath it. Dueto this self-alignment and the short channel formed by the thickness ofthe dielectric material, a high-performance FET is produced without therequirement of high-resolution lithography equipment.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not bylimitation in the accompanying figures in which like reference numeralsindicate similar elements and in which:

FIG. 1 is a cross-sectional view of an organic FET transistor includingan insulating substrate, organic polymer film, dielectric layer, andconductive gate according to the prior art;

FIG. 2 is a cross-sectional view of an vertical FET transistor includingan insulating substrate, organic polymer film, dielectric layer, andconductive gate according to the prior art;

FIG. 3 is a cross-sectional view of an vertical FET transistor accordingto the prior art illustrating the consequences of poor alignment betweenthe metal and dielectric layers;

FIG. 4 is a cross-sectional view illustrating the “V-grove” method ofachieving self-alignment between metal and dielectric according to theprior art;

FIG. 5 illustrates a structure to produce vertical organic FETtransistors according to one embodiment of the present invention;

FIG. 6 illustrates a structure to produce vertical organic FETtransistors with separate gate, source and drain terminals according toanother embodiment of the present invention;

FIGS. 7-13 illustrate the various process steps to produce the structureaccording to one embodiment of the present invention; and

FIGS. 14-15 illustrates the method by which contact holes forinterconnecting metal layers are integrated into the process accountingto another embodiment of the present invention.

DETAILED DESCRIPTION

Referring now to FIG. 5, one embodiment of this invention isillustrated. The structure is formed by depositing successive patternedlayers of a conductor metal—source 502, a first insulator dielectric504, a conductor metal-drain 506, a semiconductor 508, a secondinsulator dielectric 510, a conductor metal-drain 512 and a conductormetal-gate 514 on substrate 550.

Referring to FIG. 5, region 520 signifies a transistor formed by thisstructure. The source of this device is formed by metal source 502, andthe drain is formed by metal-drain 506. The vertical space betweenmetal-drain 506 and metal-source 502 forms the channel region 530 of thedevice in region 520. The channel region 530 is overlapped by successivelayers of a semiconductor 508, dielectric 2510, and metal gate 514. Thegate terminal of the transistor in region 520 is metal-gate 514.

Referring to FIG. 5, region 522 signifies a second transistor formed bythe same structure. The gap 540 is the channel of this transistor. Inthis implementation, the transistors 520 and 522 share the sameelectrical connection for the gate terminal. The drain terminal and thesource terminal are electrically independent terminals.

FIG. 6 illustrates another implementation of this invention in which themetal-gate layer and the metal-source layer are not continuous betweenregions 620 and 622. This structure, therefore, has electricallyindependent source, drain, and gate terminals.

FIG. 7 illustrates the beginning of the process to form the structuredescribed above. A conductor metal-source 702 is deposited on substrate750. The particular implementation in this illustration shows acontinuous layer, but this layer is typically patterned to formindependent source terminals for each transistor. The preferred methodof patterning is achieved by additive methods such as gravure,flexography, ink jet painting, or offset lithography. Materials suitablefor the metal-source can be any solution-based conductor, includingflake silver ink, flake gold ink, nano-particle silver ink,nano-particle gold ink, PEDOT, polythiophene, and polyanalene.Alternatively, this patterning can by achieved through a subtractiveprocess whereby the substrate is first coated by methods such as adoctor-blading, followed by a patterning step via etching, lift-off,laser ablation, or otherwise remove unwanted material. Subtractivemethodology can also be used for conductor metals using non-printabledeposition techniques such as evaporation, sputtering, and sublimation.

Still referring to FIG. 7, a patterned dielectric layer 704 isdeposited. The preferred method of patterning is achieved by depositinga solution-based dielectric using additive methods such as gravure,flexography, ink jet painting, or offset lithography. Alternatively,this patterning can by achieved through a subtractive process wherebythe substrate is first coated by methods such as evaporation,sputtering, sublimation, or doctor-blading, followed by a patterningstep via etching, lift-off, laser ablation, or otherwise remove unwantedmaterial.

The slope of the edges 705 of the first dielectric layer 754 is animportant consideration in the formation of this structure sincesubsequent layers will form the active transistors on this surface. Whenusing an additive deposition method, this slope can be controlled byappropriately adjusting the surface tension of the dielectric solutionand the surface energy of the underlying deposition surface. The surfacetension of the ink can be modified by methods such as adding surfactantsand by adjusting the weight-to-solid ration of the solution. The surfaceenergy of the surface to be deposited can be modified by methods such ascorona treatment, oxygen plasma, ultra-violet exposure, and ozonetreatments.

FIG. 8 has the same layers as the previous figure, like layers labeledwith like numbers. In particular, a metal-source layer 802 and adielectric layer 804 is deposited on substrate 850. The next layer isdeposited by coating the surface of a flat print plate or a rotary printroll with conductive ink. The conductive ink could be solution-basedflake conductor ink, solution-based nano-particle metal ink, PEDOT,polyanalyene, polythiophene, or some other solution-based conductivefluid. The print pressure of the print plate and the materials of whichthe print plates are formed are appropriately adjusted such that the inkwill transfer onto the raised surface formed by the first dielectric804, but such that it will not transfer into the troughs between theraised surface formed by the dielectric pattern. This mechanism willresult in a self-aligned metal coating onto the first dielectric,thereby eliminating the need to align two layers by other means such asoptical alignment.

FIG. 9 illustrates the intended behavior of the metal ink that coatedtransfer device 949. The ink that touches the raised surfaces formed bydielectric 904 sticks to the surface of that dielectric. The troughformed between the raised dielectric surfaces are sufficiently deep thatthe ink does not penetrate inside the trough. When transfer device 949is lifted, the conductive ink 905 corresponding to the regions of thetoughs remains on the transfer device, and does not transfer onto thesurface of the circuit.

FIG. 10 shows the resulting structure after the self-aligned metaldeposition is complete. Metal-source 1002, first dielectric layer 1004,and metal-drain 1006 are now deposited on substrate 1050. Themetal-drain 1006 is self-aligned with the edge of dielectric 1004.

FIG. 11 illustrates the next processing step in this process, thedeposition of the semiconductor layer 1108. This layer can be continuousas shown in the FIG. 11, but could also be patterned. The functionalrequirement is that the semiconductor is deposited on the verticalsurface 1130 and 1140 on first dielectric 1104, between metal-drain 1106and metal-source 1102. This area will become the channel region of thetransistor. Semiconductor materials include low molecular materials suchas pentacene, hexithiphene, TPD, and PBD and polymer materials such aspolythiophene, parathenylene vinylene, and polyphenylene ethylene.Hybrid materials such polyvinyl carbazole are also good candidates forthe semiconductor materials. Deposition methods include additive methodssuch as flexography, gravure, silk screening, or offset lithography.Deposition methods also include subtractive methods such as coatingmethods, evaporation, sputtering, and sublimation.

FIG. 12 illustrates the deposition of the second dielectric 1210. Thislayer must enclose the semiconductor pattern 1240. The dielectricmaterial is preferably a material that is printable, such materialsincluding inorganic precursors such as spin-on-glass or polymer-baseddielectric such as cross-linked polyvinylphenol (PVP), polypropylene,CYTOP, polyvinylalcohol, polyisobutylene, PMMA, polyethyleneterephthalate (PET), poly-p-xylylene, and CYMM. Alternatively, thedielectric could be a material that is evaporated, sputtered or grownthrough thermal and chemical reactions, and subsequently patterned byetching or laser ablation. Deposition methods include additive methodssuch as flexography, gravure, silk screening, inkjet printing or offsetlithography. Deposition methods also include subtractive methods such ascoating methods, evaporation, sputtering, and sublimation.

FIG. 13 illustrates the deposition of metal-gate 1314. This layer mustbe patterned to reside on the surface of the second dielectric 1310. Inorder to be electrically functional, this metal layer must cover thesecond dielectric layer 1310 along the channel of the transistorsdefined by edges 1330 and 1340 in FIG. 13. This layer acts as a gateterminal of the transistor, controlling the number of charge carriersthat flow through the transistor from source to drain.

The above description illustrates the formation of the transistors. In acomplete circuit design, these transistors are interconnected byconnecting appropriate metal-gate regions, metal-drain regions, andmetal-source regions through openings in the first dielectric and thesecond dielectric, as shown in FIG. 14. Opening 1411 in the seconddielectric 1410 and semiconductor layer 1404 forms a connection betweenmetal-gate 1414 and metal-source 1402 of the transistor whose channel isdefined by 1440. These holes can be formed by leaving the hole when thedielectric and semiconductor is printed, or producing them through asubtractive process including laser ablation, etching or lift-off. Ifthe holes are of appropriate size and the conductive ink is sufficientlylow in viscosity, the dielectric ink will flow into these holes. Itshould be noted that when this technique is used to make contact throughthe contact holes, a contact hole from metal-drain layer 1406 tometal-source layer 1402 is not permitted. The metal-drain layer 1406 isformed in a self-aligned manner to the raised surfaces, and willtherefore not flow into contact holes formed on that layer. From thecircuit design point of view, this does not constitute a limitationsince electrical contact since electrical contact between metal-drain1406 and metal-source 1402 can still be made by forming two contacts toproduce that connection. As illustrated in FIG. 14, opening 1412 forms aconnection between metal-gate 1414 and metal-drain 1406 and opening 1411forms a connection between the same node metal-gate 141 and metal-source1402, thereby forming an electrical contact between metal-source 1402and metal-drain 1406.

Alternatively, these contact holes can be plugged with by injectingconductive solution into the holes through methods such as inkjetprinting. Vector-based inkjet printing with a low-viscosity conductiveink will be particularly effective since the walls around the contactholes will contain the conductive fluid. Plugging can also be achievedby electroplating since regions where thicker metal is not desired iscovered by dielectric material, thereby protecting those areas from theelectroplating agent. Electroless plating can also be used utilized as amethod of filling the contact holes with conductive materials. Whencontact holes are plugged with a conductor, contact holes frommetal-drain 1511 and metal-source 1502 are permitted, as illustrated inFIG. 15.

The layer thickness of the first dielectric layer 1504 determines thechannel length of the transistor. As long as short channel lengtheffects of the transistor are appropriately managed and are tolerable,layer thicknesses as thin as 50 nm or even thinner are possible. Itshould be noted that such thin depositions require that the depositionmeans of metal-drain 1511 described above is well enough engineered notto inadvertently deposit metal in the trough formed by the dielectric,which becomes very shallow at such thin first dielectric layerthicknesses. On the other extreme, the thickness of the first dielectric1530 could be on the order of tens of microns. Though the transistordevice produced in this manner would result in lower on-current due tothe increased channel length, the deposition method would not need to beas well engineered when the trough is that deep. A typical firstdielectric thickness is in the range of 1-3 μm. Another thicknesscritical to device performance is the second dielectric, which is in therange of 100 nm to 500 nm thick, but could be thicker depending on thetransistor performance target, or could be thinner provided the layercan be reproducibly deposited without pinholes. The thickness of otherlayers have only secondary effects on the transistor behavior, andtherefore have very large ranges associated with them. Typicalthicknesses of the semiconductor 1508, metal-drain 1511, metal gate 1514ranges from 50 nm to 1 μm, but could be thicker or thinner depending onthe precision of the deposition means and the transistor performancetarget.

While the invention has been described in detail in the foregoingdescription and illustrative embodiment, it will be appreciated by thoseskilled in the art that many variations may be made without departingfrom the spirit and scope of the invention. Thus, it may be understood,for example, that the structures above could include self-assembledmonolayers (SAMs), corona treatment, or other surface treatments toobtain desired surface energy and contact angles for optimized printcharacteristics. The conductor layers may contain another conductivelayer under the first conductor, second conductor, or third conductorlayers in order to promote enhanced adhesion, or to increase or decreasewetting of the print surface. Metal layers may be treated with goldimmersion or thiol processing to reduce oxidation, increase theeffective work function of the metal, and promote desired alignment ofthe semiconductor polymer and crystalline structures. Dielectric layersmay consists of two or more layers in order to promote adhesion, reduceleakage through the dielectric, alter the capacitance of the dielectriclayers, or to enhance the capability of controlling the slope on theedges of the dielectric. Various curing steps either at each depositionstep or at the end of the entire process may also be included.

We claim:
 1. An organic field-effect transistor comprising: a patterneddielectric layer having a raised surface; a source or drain conductorlayer; and a vertical transistor structure, wherein the source or drainconductor layer is deposited as a self-aligned layer to the underlyingdielectric layer by applying the conductor layer only to the raisedsurface of the dielectric layer.
 2. An organic field-effect transistorcomprising: a substrate layer; a metal source layer formed on thesubstrate layer; a first dielectric layer formed on the substrate layerhaving a sloped edge, the sloped edge forming the channel length of thetransistor; a self-aligned metal drain layer formed on the firstdielectric layer; a semiconductor layer formed on the sloped edge of thefirst dielectric layer; and a metal gate layer formed on thesemiconductor layer.
 3. The organic field-effect transistor of claim 1further comprising openings in the semiconductor and second dielectriclayers to allow contact to the metal source layer.
 4. The organicfield-effect transistor of claim 1 further comprising openings in thesemiconductor and second dielectric layers to allow contact to the metaldrain layer.
 5. A method of fabricating an organic field-effecttransistor comprising: forming a substrate layer; forming a metal sourcelayer on the substrate layer; forming a first dielectric layer on thesubstrate layer having a sloped edge, the sloped edge forming thechannel length of the transistor; forming a self-aligned metal drainlayer on the first dielectric layer; forming a semiconductor layerformed on the sloped edge of the first dielectric layer; and forming ametal gate layer formed on the semiconductor layer.
 6. The method ofclaim 5 further comprising forming openings in the semiconductor andsecond dielectric layers to allow contact to the metal source layer. 7.The method of claim 5 further comprising forming openings in thesemiconductor and second dielectric layers to allow contact to the metaldrain layer.
 8. The method of claim 5, wherein forming the self-alignedmetal drain layer comprises: coating the surface of a print plate withink comprising a solution-based conductor; and applying the print plateto transfer the ink to a raised surface of the first dielectric layer,but not transferring the ink to troughs in the first dielectric layer.9. The method of claim 8, wherein the pressure of the print plate isadjusted to optimize ink transfer only to a raised surface of the firstdielectric layer, the optimized pressure being evidenced by asubstantial lack of ink in the troughs in the first dielectric layer.10. The method of claim 8, wherein the material of the print plate ischosen to optimize ink transfer only to a raised surface of thedielectric, the optimized plate material being evidenced by asubstantial lack of ink in the troughs in the first dielectric layer.11. The method of claim 8, wherein the slope of first dielectric layeredge is controlled by adjusting the surface tension of the ink used toform the first dielectric layer and the surface energy of the metalsource layer.
 12. The method of claim 11, wherein the surface tension ofthe ink used to form the first dielectric layer is modified by addingsurfactants or by adjusting the weight-to-solid ratio of the inksolution.
 13. The method of claim 1 wherein the surface energy of themetal source layer is adjusted through corona treatment, oxygen plasmatreatment, ultra-violet exposure, ozone treatments, or application of amaterial designed to modify the surface energy.
 14. The method of claim5 further comprising forming a first organic field-effect transistor, asecond organic field-effect transistor, and a metal gate layer common tothe first and second organic field-effect transistors.
 15. The method ofclaim 5, wherein the metal source layer is formed using a solution-basedconductor, including flake silver ink, flake gold ink, nano-particlesilver ink, nano-particle gold ink, PEDOT, polythiophene, andpolyanalene.
 16. The method of claim 8, wherein the print plate iscoated with a conductive ink comprising a solution-based flake conductorink, solution-based nano-particle metal ink, PEDOT, polyanalyene,polythiophene, or other solution-based conductive fluid.
 17. The methodof claim 5, wherein the semiconductor layer is formed using lowmolecular materials comprising pentacene, hexithiphene, TPD, and PBD.18. The method of claim 5, wherein the semiconductor layer is formedusing polymer materials comprising polythiophene, parathenylenevinylene, and polyphenylene ethylene.
 19. The method of claim 5, whereinthe semiconductor layer is formed using hybrid materials comprisingpolyvinyl carbazole.
 20. The method of claim 5, wherein the seconddielectric layer is formed using a printable material comprisingspin-on-glass or a polymer-based dielectric comprising cross-linkedpolyvinylphenol (PVP), polypropylene, CYTOP, polyvinylalcohol,polyisobutylene, PMMA, polyethylene terephthalate (PET),poly-p-xylylene, and CYMM.